Typically, such memory arrays comprise memory modules arranged in a repetitive manner. For example, for a 4-Mbit embedded DRAM-type memory, thirty-two 128-Kbit modules are associated. Each memory module generally includes a local controller, which communicates with an overall activity controller. The overall activity controller is used to monitor the activity of each module based on information supplied by each local controller, in order to launch an operation for any one of the modules only when all the modules are inactive.
In other words, when one or more of the memory modules has begun an operation, the overall activity controller waits for completion of the operation before beginning an operation for one of the other modules. The memory may therefore wait for the last module activated, or the slowest, to have completed its operation before activating another module. To implement this control, each local controller is connected to a common bus, to which the overall activity controller is also connected to.
Typically, each local controller includes a 3-state buffer circuit receiving, as input, an activity signal obtained from the memory module and delivering to the control bus a control signal, the level of which reflects the activity of the module being monitored. When the memory module is inactive, the control bus is set to high impedance. A new activity is ready to be launched when all the memory modules are inactive. At the start of activity, the control signal is set to “0”, whereas at the end of activity, the control signal is set to “1”.
This type of control is largely dependent on the size of the memory array, such that, when the size of the memory increases, the performance falls. In practice, when the size of the memory increases, the buffer circuits may be dimensioned accordingly, which means a consecutive dimensioning of the control bus so that it is difficult to reach the target speed.
Moreover, when a memory module is situated at a great distance from the overall activity controller, the resistive effect in the control bus further reduces the speed of the memory so that, before activating a module of the memory array, the overall activity controller may often wait for the module situated furthest away, which is not necessarily the slowest, to indicate an end of its activity. It has also been observed that the complexity of the controller increases exponentially with gains in performance.